1. Field of the Invention
This invention relates to a clock generator suitable for use with circuits operating under control of clock signals.
2. Description of the Prior Art
A conventional application of such a clock generator is, for example, a dynamic random access memory circuit (RAM) as shown in FIG. 1. Another example of a RAM different from that in FIG. 1 is illustrated in FIG. 2 as will be discussed later.
In FIG. 1, each of single bit memory cells 1 consists of a storage capacitor 2 for storing "1" or "0" data and a switching transistor 3 for reading, writing or holding the data in the storage capacitor 2. Switching on and off the respective one of the switching transistors 3 is controlled by a control signal fed via the corresponding one of word lines 5. The data read from the respective memory cells 1 pass through a common bit line 4. The data in the bit lines 4 are amplified by a sense amplifier 6. A respective one of decoders 7 as defined by a phantom line selects one of a plurality (2.sup.n in the illustrated example) of the memory cells 1 connected to the common bit line 4. In the respective decoder 7, a terminal 8 is supplied with an address signal A.sub.1, A.sub.1, A.sub.2, A.sub.2, . . . , A.sub.n, A.sub.n (these are sometimes collectively referred to as "A"). Each of transistors 9 works in response to the address signal A applied thereto. A line 10 is a first output line of the decoder 7, a terminal 11 is one which is supplied with a pre-charge signal .phi. for pre-charging the output line 10, and a terminal 13 is a power terminal. A transistor 12 is a switching transistor for pre-charging the output node 10. In response to a level at the output node 10, a transistor 14 couples with the word line 5 a clock output signal .phi..sub.2 fed via a line 15 from a clock generator 21. Address buffer circuits 17 shown at the extreme left of the drawing are responsive to an address input signal a.sub.1 -a.sub.n assigning the address of the respective memory cell 1 to generate a pair of complementary address signals A.sub. 1, A.sub.1 -A.sub.n, A.sub.n. A signal .phi..sub.1 which enables the address buffer circuit 17 is supplied via a respective terminal 20. The output signal of the address buffer circuit 17 is outputted from two output terminals 18 and 19. The signal .phi..sub.1 is also fed via a terminal 22 to the clock generator 21 which generates the clock output signal .phi..sub.2 to enable the decoders 7.
Referring to the waveforms of the respective signals .phi., .phi..sub.1, A.sub.1, A.sub.1 -A.sub.n, A.sub.n, x, .phi..sub.2 and a.sub.1 -a.sub.n as depicted in FIG. 3, operation of the RAM of FIG. 1 will now be described.
During the period when the pre-charge signal .phi. is "1", the outputs of the respective address buffer circuits 17 are "0". When the pre-charge signal .phi. goes to "0", the signal .phi..sub.1 goes to "1" so that the address signals A.sub.1, A.sub.1, . . . , A.sub.n, A.sub.n, that is, the outputs of the address buffer circuits 17 are determined by the address inputs a.sub.1 -a.sub.n. Those address signals A from the address buffer circuits 17 are fed to the respective decoders 7.
Assume now that the address inputs a.sub.1 -a.sub.n all are "0" and that the address signals A.sub.1 -A.sub.n are "0" with A.sub.1 -A.sub.n being "1".
In such a case, all of the output lines 10 in the plurality of the decoders 7 pre-charged with the pre-charge signal .phi. except the uppermost of the decoders in FIG. 1 are discharged to "0" response to the address signals A. This is because the address signals A.sub.1 -A.sub.n of a "1" level are provided to all of the decoders 7 except the uppermost of the decoders 7.
Since under these circumstances only the transistor 14 in the uppermost of the decoders 7 is turned ON, when the clock output signal .phi..sub.2 goes to "1" a voltage is supplied only to the word line 5 in the uppermost memory 1 by way of that transistor 14 so that a data is read from that designated memory cell 1 via the bit line 4. The sense amplifier 6 then amplifies the data to complete reading the data from the memory.
Then the clock output signal .phi..sub.2 is generated by the clock generator 21 when discharging of the output lines 10 in the respective decoders 7 is almost over. The reason is that, provided that the clock output signal .phi..sub.2 is developed before discharging the respective output lines is completed, the clock output signal .phi..sub.2 is fed with all of the transistors 14 being in the ON state so that the word lines other than those duly addressed by the address inputs a.sub.1 -a.sub.n are supplied with a voltage to select memory cells 1 other than the duly addressed one (i.e. multiplex selection). Should the length of time from the completion of data reading from the memory to the development of the clock output signal .phi..sub.2 be extended, the memory would not face the above discussed problem but would require a long time to complete data reading after being addressed (that is, long access time). It is therefore most desirable that the clock output signal .phi..sub.2 be generated immediately after the output nodes 10 of the decoders 7 have been discharged.
FIG. 4 is a circuit diagram showing in detail an example of the conventional clock generator 21 schematically depicted in FIG. 1. In FIG. 4, the signal .phi..sub.1 is applied to terminals 31 and the pre-charge signal .phi. to a terminal 33, while the clock output signal .phi..sub.2 is delivered from an output terminal 32. A driver circuit section 34 and a delay circuit section 35 are denoted by the phantom line, respectively. A transistor 36 in the driver circuit section 34 is a charging transistor for the output of the driver circuit and another transistor 37 is a discharging transistor therefor. A boosting capacitor 38 is to boost the voltage at node 40, decrease the ON resistance of the charging transistor 36 and increase the charging speed. A transistor 39 is to shut off supply of the signal .phi..sub.1 to the node 40 during voltage boosting. A transistor 42 in the delay circuit section 35 is one for discharging an output line 41 from the delay circuit 35, while another transistor 43 is one for charging the output line 41. Furthermore, a transistor 44 is to discharge a charging line 46 and another transistor 45 is to charge the charging line 46. A power supply terminal is denoted by 47.
Within the above circuit arrangement, the output terminal 32, the charging line 46 and the node 40 are held "0" and the output line 41 is held "1" when the pre-charge signal .phi. is "1". At the moment where the signal .phi..sub.1 goes to "1", the node 40 is brought up to a "1" level but the output terminal 32 is still held at a "0" level due to a ratio of the ON resistances of the charging and discharging transistors 36 and 37 since the output line 41 is still at a "1" level. Upon receipt of the signal .phi..sub.1 assuming the "1" level, the transistor 45 is turned ON and the voltage at the charging line 46 changes from "0" to "1". As soon as the charging line 46 goes to the "1" level, the transistor 42 starts turning ON and the voltage at the output line 41 starts dropping from the "1" level to the "0" level. If the voltage level at the output line 41 drops below the threshold voltage of the discharging transistor 37, then the discharging transistor 37 is turned OFF and the voltage at the output terminal 32 starts rising. In other words, the clock output signal .phi..sub.2 begins appearing.
The length of time extending from the time when the signal .phi..sub.1 becomes "1" to that when the clock output signal .phi..sub.2 begins appearing is dependent upon the operation time of the delay circuit section 35. Therefore, through adjustment of the delay time of the delay circuit section 35, an improved RAM circuit is attained which operates at high speed without multiplex selection.
For RAM circuits, it is generally required to operate normally within about .+-.10% fluctuations of the power voltage V supplied thereto. The delay time should therefore be determined in consideration of such fluctuations of the power voltage V.
Insofar as the discharging timing of the decoders 7 and the developing timing of the clock output signal .phi..sub.2 from the clock generator 21 have the same dependency on the power voltage, timing selection may be made with any suitable power voltage. However, the same dependency is not easily available due to dispersion of pattern layouts on chips. In particular, the discharge time of the decoders 7 is primarily determined by the resistance of aluminum lines, N.sup.+ diffusion resistances and so forth which are not dependent upon the power supply voltage V, whereas the delay time of the clock generator 21 is primarily determined by the resistance of MOS transistors which are dependent upon the power supply voltage V.
In FIG. 5 the power voltage dependency of the discharge time t.sub.1 of the decoders 7 and the power voltage dependency of the delay time t.sub.2 of the clock output signal .phi..sub.2 are plotted with the solid lines I and II, respectively. As shown herein, the dependencies I and II are such selected that t.sub.1 is equal to t.sub.2 at a normal value V of the power supply voltage. It is noted that the operation times of both the circuits tend to decrease with increase in the power supply voltage V.
It is evident from FIG. 5 that t.sub.1 &gt;t.sub.2 with a power voltage higher than the normal value V and the clock output signal .phi..sub.2 is developed prior to discharging of the decoders, thus faulty operation of the RAM is caused by the multiplex selection of the memory cells 1.
To avoid this, the dependencies I and II may be selected such that t.sub.1 =t.sub.2 at the +10% point A as suggested by the dot line in FIG. 5. In this case the reading speed of the RAM becomes slow because the clock output signal .phi..sub.2 is developed with a delay t.